This invention relates to a method for forming metal films as part of high-density metallization processing of particular utility in integrated circuit semiconductor device and circuit board manufacture, which process employs "damascene" (or "in-laid") technology.
Metal films of the type contemplated herein are used, e.g., in "back-end" semiconductor manufacturing technology, to form electrically conductive contacts to active as well as passive device regions or components formed in or on a semiconductor substrate, as well as for filling via holes, interlevel metallization, and interconnection routing patterns for wiring together the components and/or regions. Metals employed for such purposes include, inter alia, titanium, tantalum, tungsten, aluminum, chromium, nickel, cobalt, silver, gold, copper, and their alloys. Of these, copper and copper-based alloys are particularly attractive for use in large-scale integration (LSI), very large-scale integration (VLSI), and ultra large-scale integration (ULSI) semiconductor devices requiring multilevel metallization systems for "back-end" processing of the semiconductor wafers on which the devices are based. Copper and copper-based metallization systems have very low resistivities, i.e., lower than those of previously preferred systems utilizing aluminum and its alloys, as well as significantly higher resistance to electromigration. Moreover, copper and its alloys enjoy a considerable cost advantage over a number of the above-enumerated metals, notably silver and gold. Also, in contrast to aluminum and the refractory-type metals included in the above listing, copper and its alloys can be readily deposited in good quality, bright layer form by well-known electroplating techniques, at deposition rates fully compatible with the requirements of device manufacturing throughput.
Referring now to FIG. 1, schematically shown therein in cross-sectional view is a conventional damascene processing sequence for forming recessed (i.e., "in-laid") metallization patterns such as, for example, "back-end" contacts, vias, interconnections, routing, etc., in a semiconductor device formed in or on a semiconductor wafer substrate 1. In a first step, the desired conductor pattern is defined as a pattern of recesses 2 such as grooves, trenches, holes, etc., formed (e.g., by etching) in the surface 4 of a dielectric layer 3 deposited or otherwise formed over the semiconductor substrate, followed by a second step comprising deposition of a suitably conductive metal layer 5 filling the etched recesses 2. Typically, in order to ensure complete filling of the recesses, the metal layer 5 is deposited as a blanket (or "overburden") layer of excess thickness t so as to overfill the recesses 2 and cover the exposed upper surface of the dielectric layer 3. Next, the entire excess thickness t of the metal overburden layer 5 over the surface of the dielectric layer 3 is removed using a chemical-mechanical polishing (CMP) process comprising moving the wafer while urging the wafer surface into contact with a facing surface of a polishing pad and providing a slurry comprising abrasive particles in the area of contact. As a result of such polishing, the portions of the overburden layer 5 overlying the surface 4 of the dielectric layer 3 are substantially completely removed, while metal portions 5' remain in the recesses 2 with their exposed upper surfaces 6 substantially co-planar with the surface 4 of the dielectric layer 3. Thus this conventional process, termed "damascene process" forms in-laid conductors 5' in the dielectric layer while avoiding problems associated with other types of processes, e.g., metal etching and dielectric gap filling.
Such damascene processing as described above can be performed with a variety of other types of substrates, e.g., printed circuit boards, with and/or without intervening dielectric layers, with a plurality of metallization levels (i.e., up to five at present), and with any of the previously enumerated metals. However, the parallel drives toward cost reduction and increased microminiaturization of semiconductor devices have provided impetus for greater utilization of copper or copper-based metallization/interconnection metallurgy, particularly in view of the above-described advantages obtainable thereby. The use of copper-based metallurgy, however, has presented several problems and drawbacks, including the possibility of copper diffusion into the semiconductor substrate (typically silicon) and poor adhesion to various dielectric materials (typically oxides and/or nitrides of silicon), necessitating provision of an adhesion promoting and/or diffusion barrier layer (e.g., of chromium, tantalum, or tantalum nitride) prior to deposition of copper-based metallization.
Another problem associated with damascene processing of metallic materials, including copper and its alloys, arises from the phenomenon of increased rates of erosion by CMP of high-density conductor patterns, i.e., patterns wherein the surface coverage by the layer of electrically conductive material forming the pattern is above about 80% of the available surface area, e.g., 80-90% coverage as is typical in current semiconductor technology. As will be described in more detail below, such increased erosion rates of regions of high density metallization patterns by CMP, vis-a-vis erosion rates of regions of lower metallization density or which are free of metallization, also results in greater erosion of the dielectric layer portions intermediate the metallization features. As a consequence, non-planarity occurs across the surface of a wafer substrate in at least rough correspondence to the pattern of high and low density metallization regions.
The above-described phenomenon will now be described in more detail with reference to FIGS. 2-3, which are simplified schematic-cross-sectional "before CMP" and "after CMP" views, respectively, of a portion of an intermediate device structure 10 subjected to damascene processing for forming an in-laid metallization pattern therein, and in which like reference numerals are used as previously to designate like features.
More particularly, as shown in the "before CMP" view of FIG. 2, a typical intermediate structure 10 prepared for damascene type "back-end" metallization processing may include a plurality of types of surface regions, designated, for illustrative purposes only, as regions A, B, and C of a substrate comprising a semiconductor wafer 1. For descriptive purposes, a region hereinafter characterized as a "relatively high-density region" denotes a region wherein a metallization pattern occupies more than 80% of the available surface area of the region, e.g., 80-90% of the available surface area. As a corollary, a region which comprises a metallization pattern occupying less than about 80% of the available surface area is denoted as a "relatively low-density" region. A region which contains substantially no recesses is designated as "recess-free".
As illustrated in FIG. 2, a relatively low recess density first type region A of intermediate structure 10 comprises a single recess 2 extending for a depth into dielectric layer 3. A relatively high recess density second type region B comprises a plurality of relatively closely-spaced recesses 2 extending for a similar depth into dielectric layer 3 and may, for example, form part of an interconnection or routing pattern or circuit. Substantially recess-free third type region C is not subjected to metallization patterning.
Intermediate structure 10, prepared by conventional technology such as has been previously described with reference to FIG. 1, comprises dielectric and metal overburden layers, 3 and 5, respectively, of substantially uniform thickness across the surface area of semiconductor wafer substrate 1. That is, dielectric layer thicknesses d.sub.1, d.sub.2, and d.sub.3, of respective first, second, and third type regions A, B, and C, are substantially equal, as are the corresponding metal overburden layer thicknesses t.sub.1, t.sub.2, and t.sub.3. The required, or design, thickness of the planarized metallization segments or portions 5' filling the recesses 2' of the second type region B is designated by reference letter m.
When fabricated according to the design requirements of current semiconductor device technology, the relatively high recess density second type region B of intermediate structure 10 comprises a large plurality of recesses 2', limited to four in the drawing for illustrative simplicity, spaced apart by about 0.18-0.5 .mu.m and having widths and depths of about 0.8-2.0 .mu.m and 0.3-2.5 .mu.m, respectively. Metal overburden layer 5 may have a thickness of about 1.5 .mu.m and dielectric layer may have a thickness of about 0.3-1.0 .mu.m, depending upon the particular dielectric material and device design requirements.
Referring now to FIG. 3, shown therein is a cross-sectional schematic view of the same portion of intermediate structure 10 as in FIG. 2, but after removal of metal overburden layer 5 according to conventional chemical-mechanical polishing (CMP) technology in order to form in-laid conductor segments or portions 5'. As is apparent from the figure, because of the previously noted phenomenon associated with CMP of high density metal segments, a greater thickness of metal overburden layer 5 has been eroded in the relatively high recess density second type region B than in the relatively low recess density first type region A and the substantially recess-free third type region C.
As a consequence of the increased erosion of the metal overburden layer 5 in the relatively high recess density second type region B, the portions of the dielectric layer 3 filling the spaces between adjacent recesses 2' of the region are also subjected to increased erosion relative to the portions of dielectric layer 3 of the first and third type regions A and C, respectively. Thus, whereas the dielectric layer 3 thicknesses d.sub.1 and d.sub.3 of first and third type regions A and B, respectively, are unaffected by the CMP processing, both thickness d.sub.2, of dielectric layer 3 and thickness m' of the planarized metallization segments or portions 5' are reduced during the CMP processing. The effect of increased erosion of both components of region B is non-planarity of the overall polished surface due to formation therein of a concavity 11 of average depth d.sub.4 below the surface 4 of the dielectric layer 3 in regions A and C.
In general, the depth d.sub.4 of concavity 11 will depend upon a number of factors, including the particular metallization metal, its density in region B, and the CMP conditions, such as pad hardness, applied pressure, type of abrasive particles, slurry additives, etc., and must be determined for each particular application.
The formation of concavity 11 incurs a further consequence arising from the reduction of the thickness of the metal layer portions of the metallization segments 5', i.e., lower conductivity metallization patterns, often less than design or minimum acceptable values. Moreover, the concomitantly reduced thickness of the dielectric layer 3 adversely affects interlevel isolation, and can result in other deleterious effects such as crosstalk and RC time constant signal delay. In addition, and very significantly, the negative effects of such non-planarity are exacerbated in multi-level metallization schemes such as are required for LSI, VLSI, and ULSI devices.
Thus, there exists a need for a method for forming high-density in-laid metallization patterns by a damascene-CMP technique which does not suffer from the problems and drawbacks of the prior art, i.e., non-planarity, reduced electrical conductivity of the metallization features, and reduced dielectric isolation resulting in degradation of device properties. Specifically, there exists a need for an improved electroplating and CMP-based metallization method for forming, by damascene techniques, high-density, in-laid, copper-based "back-end" contacts, vias, interlevel metallization, and interconnect routing of active devices (e.g., transistors) and/or other components in integrated circuit semiconductor devices. Moreover, there exists a need for an improved electroplating and CMP-based method which is fully compatible with conventional process flow, methodology, and throughput requirements in the manufacture of such integrated circuit semiconductor devices and other devices requiring in-laid metallization patterns.